Manufacturing process variations have emerged as the primary cause of performance degradation in today's integrated circuit systems (ICs). The variations cause a significant spread in the performance of the manufactured integrated circuits (ICs). This translates into a significant increase in uncertainty in the performance of manufactured integrated circuits. The variations in the integrated circuit components viz., the CMOS devices and metal interconnects are a manifestation of the inherent randomness associated with some of the semiconductor fabrication process steps. For example, the metal interconnect thickness is determined by the composition of the slurry used in the chemical mechanical polishing step of the fabrication process along with the quality of the pad used for polishing. The variations in the effective channel length of the CMOS devices are determined by the effectiveness of the critical dimension (CD) control ability of the fabrication process. The variations in various CMOS device parameters such as gate oxide thickness, dopant density and threshold voltages; and the variations in the metal interconnect width and thickness etc., result in variations in the circuit performance characteristics such as a CMOS gate delay time and voltage response, a CMOS gate active and leakage power consumption, a metal interconnect delay time and voltage response etc. Hence, efficient techniques are required for an accurate analysis of the integrated circuit performance in the presence of these variations. This integrated circuit performance analysis requires that delay time, power and voltage response models be developed for the CMOS gates, metal interconnects and other components of the integrated circuits.